At 5G and millimeter-wave (mmWave) operating frequencies—typically spanning 24 GHz to 77 GHz and above—controlling signal attenuation is a baseline requirement for functional hardware. In high-speed and radio-frequency (RF) circuits, signal degradation is primarily driven by two interrelated phenomena: insertion loss (the overall drop in signal power as it travels through a transmission line) and return loss (the power reflected back toward the source due to impedance mismatches).
Minimizing these losses requires matching the circuit’s physical geometry to the electromagnetic behavior of high-frequency fields. The dominant factors governing this performance include dielectric material properties (Dk and Df), copper surface roughness relative to the RF skin depth, transmission line geometry, surface finish electrical conductivity, and manufacturing tolerances such as trace etching accuracy.
Successfully deploying a high-performance high speed PCB requires addressing these physical variables early during the stackup design and design-for-manufacturing (DFM) review stages. This guide outlines the engineering mechanisms behind RF attenuation, compares low-loss substrate materials, and details the fabrication controls required to maintain clean signal propagation across millimeter-wave bands.
The High-Frequency Signal Challenge: Why Insertion Loss and Return Loss Escalate at 5G mmWave
Signal degradation increases non-linearly with frequency. While sub-6 GHz designs can tolerate standard substrate tolerances and conventional conductor profiles, mmWave frequencies introduce strict constraints on signal path continuity.
| Attenuation Component | Variable | Dominant Physical Mechanism | Mitigation Target |
| Total Channel Attenuation | $S_{21}$ | Cumulative power dissipation along the complete signal path | Balance link budget margins across the target operational bandwidth |
| Dielectric Loss | $\alpha_d$ | Dipole molecular friction and polarization dissipation in the substrate resin matrix | Select low-loss substrates with ultra-low dissipation factors ($\text{Df} \le 0.002$) |
| Conductor Loss | $\alpha_c$ | Resistive skin-effect dissipation amplified by tooth-profile copper surface roughness | Utilize sub-micron Very Low Profile (VLP) or Hyper Very Low Profile (HVLP) copper foils |
| Radiation / Leakage Loss | $\alpha_r$ | Unconfined electromagnetic fields radiating into free space or leaking between traces | Implement Grounded Coplanar Waveguides (GCPW) with continuous via fencing |
Insertion Loss ($S_{21}$): Represents total signal dissipation along the interconnect. When insertion loss is too high, eye diagrams close, bit error rates (BER) rise in high-speed digital links, and the link budget in active antenna arrays deteriorates, directly reducing radar detection range and cellular coverage.
Return Loss ($S_{11}$): Quantifies signal reflections resulting from discontinuities along the transmission path. Poor return loss degrades amplifier stability, creates standing waves, and induces inter-symbol interference (ISI).
| Loss Metric | Primary Physical Drivers | Observable System Impact | Target Design Boundary |
| Insertion Loss ($S_{21}$) | Dielectric dissipation ($\tan \delta$), copper surface roughness, trace length | Reduced RF output power, shorter transmission range, receiver sensitivity drop | Minimize overall dB/inch across the operational band |
| Return Loss ($S_{11}$) | Width variations, via stub resonance, layer transitions, dielectric thickness shifts | Standing waves, signal distortion, component overheating, power amplifier instability | Typically maintain $\le -15\text{ dB}$ to $-20\text{ dB}$ across operating band |
Root Causes of RF Attenuation: Conductor Loss vs. Dielectric Loss
Total attenuation along a printed transmission line consists primarily of dielectric loss ($\alpha_d$) and conductor loss ($\alpha_c$). Understanding the boundary conditions between these two modes determines where engineering investments should focus.
Dielectric Dissipation: Selecting the Right Dk and Df for Sub-6 GHz and mmWave
Dielectric loss occurs when the alternating electric field of an RF signal continuously polarizes the polymer molecules within the board resin, converting electrical energy into heat.
Dielectric Constant ($\varepsilon_r$ or Dk): Governs phase velocity and capacitance per unit length. Lower Dk values permit wider conductor traces for a targeted characteristic impedance (such as 50 $\Omega$), reducing resistive losses. At mmWave frequencies, Dk stability across wide temperature swings and frequency bands is essential to prevent phase distortion in phased-array antennas.
Dissipation Factor ($\tan \delta$ or Df): Dictates the efficiency of the substrate in transmitting RF energy without thermal dissipation. While standard FR-4 features Df values around $0.015$ to $0.020$ (making it unsuitable for mmWave), high-frequency laminates provide low-loss ($0.004$ to $0.007$) or ultra-low-loss ($0.0009$ to $0.002$) performance.
Skin Depth and Copper Roughness: How Microscopic Profile Dictates Conductor Loss
Conductor loss is heavily influenced by the skin effect. As frequency increases, current flow concentrates within an increasingly thin layer near the outer perimeter of the copper trace:
$$\delta = \sqrt{\frac{\rho}{\pi f \mu}}$$
At 28 GHz, the skin depth ($\delta$) in standard copper drops below $0.4\ \mu\text{m}$. When the root-mean-square (RMS) surface roughness ($R_q$ or $R_z$) of the copper foil matches or exceeds the skin depth, the current is forced to travel along the microscopic peaks and valleys of the copper profile. This lengthens the effective physical path and generates local eddy-current disruptions, increasing conductor loss ($\alpha_c$).
Standard Electrodeposited (ED) copper features excessive tooth profiles that drive up attenuation at mmWave frequencies. Minimizing conductor loss requires Very Low Profile (VLP) or Hyper Very Low Profile (HVLP) copper foils, where profile roughness is held to sub-micron dimensions.
High-Frequency Substrate Selection: PTFE, Hydrocarbon, and Hybrid Stackups
Substrate selection determines the baseline loss profile of the circuit board before manufacturing begins.
Comparing Low-Loss Laminate Families
Substrates for high-frequency boards fall into three primary material categories:
PTFE-Based Substrates (e.g., Rogers RT/duroid, Taconic): Deliver the lowest dielectric constant and dissipation factors available ($\text{Df} \approx 0.0009 – 0.0015$). However, PTFE is prone to cold flow, exhibits high z-axis coefficient of thermal expansion (CTE), and requires specialized sodium etching or plasma surface preparation prior to through-hole plating.
Ceramic-Filled Hydrocarbon Resins (e.g., Rogers RO4000 series): Offer dependable electrical performance ($\text{Df} \approx 0.003 – 0.005$) while processing similarly to conventional epoxy boards. Their mechanical behavior integrates smoothly with standard automated drilling and desmear chemistries.
Advanced Modified Epoxy/Polyphenylene Oxide (PPO/PPE) (e.g., Megtron 6/7/8): Engineered specifically for multi-channel high-speed digital and hybrid RF backplanes requiring tight thermal reliability, microvia integration, and low attenuation up to 40+ GHz.
Hybrid Multilayer Construction: Balancing Cost and High-Speed Signal Integrity
Building an entire high-layer-count board solely out of high-frequency laminates is often cost-prohibitive and mechanically complex. A reliable solution is a hybrid multilayer stackup, which places thin, ultra-low-loss laminates on the outer layers to carry critical RF lines, while using standard glass-reinforced FR-4 or mid-loss prepregs for internal power planes and low-speed digital control lines.
| Layer Level | Material Type | Functional Allocation | Signal & Mechanical Role |
| Layer 1 (Top) | High-Frequency RF Core (PTFE / Hydrocarbon) | Outer RF Transmission Lines | Carries 5G mmWave traces; minimizes $\alpha_d$ and $\alpha_c$ |
| Layer 2 | Continuous Copper Plane | Primary Ground Reference | Provides an uninterrupted return path directly below RF traces |
| Core / Prepreg | Modified FR-4 / No-Flow Prepreg | Dielectric Isolation & Bonding | Thermally compatible bonding medium; controls stackup cost |
| Layer 3 | Standard Copper Foil | Power & Low-Speed Digital | Carries DC power rails, telemetry, and baseband control routing |
| Layer 4 (Bottom) | Standard FR-4 Substrate & Copper | Secondary Ground / Shielding | Structural balancing to prevent board warpage during reflow |
When specifying hybrid laminates for high speed PCB manufacturing, close coordination with the fabricator is necessary to manage lamination cycles, resin flow compatibility, and differential thermal expansion coefficients (CTE) across the material boundaries.
Eliminating Impedance Discontinuities: How to Minimize Return Loss
Return loss is driven by step changes in characteristic impedance ($Z_0$). While broad losses are governed by the substrate, return loss spikes are typically created by geometric disruptions along the signal path.
Microstrip vs. Grounded Coplanar Waveguide (GCPW) at Millimeter Frequencies
The choice of transmission line geometry governs radiation loss, ground-loop inductance, and manufacturing tolerance sensitivity:
Microstrip: Simple to route and requires no top-layer ground balance. However, microstrip traces are prone to radiation losses at frequencies above 30 GHz and are susceptible to solder mask variations, which can alter effective Dk and degrade return loss.
Grounded Coplanar Waveguide (GCPW): Places ground planes adjacent to the signal trace on the same layer, backed by periodic ground vias. GCPW confines electromagnetic fields tightly within the coplanar gap, lowering radiation loss and decoupling the signal from adjacent conductors. Because field lines primarily cross air and top dielectric layers, GCPW helps preserve impedance stability into upper mmWave bands, provided the coplanar gap width is tightly maintained during chemical etching.
| Geometry Parameter | Microstrip Transmission Line | Grounded Coplanar Waveguide (GCPW) |
| Conductor Configuration | Single trace over a solid reference plane | Center signal trace flanked by coplanar ground planes |
| Lateral Shielding | None (Susceptible to edge-radiation and crosstalk) | Excellent (Coplanar ground pours shield adjacent lines) |
| Radiation Losses ($>30\text{ GHz}$) | Higher due to open fringing fields into air | Significantly lower; fields are tightly bound in coplanar gaps |
| Via Stitching Requirements | Standard layer-transition stitching | Dense periodic ground vias required along flanking grounds |
| Fabrication Sensitivity | Trace width ($W$) and dielectric height ($H$) | Trace width ($W$), dielectric height ($H$), and gap width ($S$) |
Via Stubs and Layer Transitions: Backdrilling and Blind/Buried Microvias
Whenever an RF or high-speed differential signal transitions across vertical board layers, the via barrel represents an electrical discontinuity:
Via Stub Resonance: Any unused portion of a through-hole via (the “stub”) acts as an open-ended transmission line. At the quarter-wave frequency ($\lambda/4$), this stub acts as a virtual short, creating severe return loss and deep notches in insertion loss transmission ($S_{21}$).
Mitigation Techniques:
Backdrilling (Controlled-Depth Drilling): Removes unused stub copper, leaving residual stubs typically below $0.2\ \text{mm}$ (subject to manufacturing tooling and layer-to-layer depth capabilities).
Sequential Lamination and Microvias: Using laser-drilled blind and buried vias eliminates stubs entirely, maintaining an uninterrupted ground reference path adjacent to the transition.
Impact of Surface Finishes on mmWave Insertion Loss
The final surface finish deposited over exposed copper traces protects pads from oxidation and provides a solderable surface. However, because skin depth is extremely small at high frequencies, the electrical conductivity and magnetic properties of this thin plating layer directly affect insertion loss.
| Surface Finish Type | Typical Layer Composition | High-Frequency Suitability | Key Considerations for mmWave Applications |
| ENIG (Electroless Nickel Immersion Gold) | $3 – 5\ \mu\text{m}$ Nickel, $0.05\ \mu\text{m}$ Gold | Poor at $>10\text{ GHz}$ | The electroless nickel layer is ferromagnetic and possesses poor electrical conductivity. Because skin depth pushes signal current through the nickel layer, insertion loss increases significantly at mmWave frequencies. |
| ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) | $3 – 5\ \mu\text{m}$ Nickel, $0.05 – 0.2\ \mu\text{m}$ Palladium, Gold flash | Moderate (Wire bondable) | Improved solderability and wire-bonding support compared to ENIG, but the presence of the nickel layer still induces measurable attenuation at high frequencies. |
| Immersion Silver (ImAg) | $0.15 – 0.4\ \mu\text{m}$ Silver directly on Copper | Excellent | Highly conductive coating deposited directly onto copper with no intermediate nickel barrier. Delivers the lowest insertion loss profile across 24 GHz to 77 GHz bands. |
| Immersion Tin (ImSn) | $0.8 – 1.2\ \mu\text{m}$ Tin directly on Copper | Good | Provides a planar, non-magnetic surface with moderate insertion loss performance, though sensitive to multiple thermal reflow profiles and storage shelf life. |
| OSP (Organic Solderability Preservative) | Ultra-thin organic polymer coating | Excellent | Leaves pure copper for signal conduction with zero metallic plating losses. However, the surface is vulnerable to handling damage and degrades across multiple lead-free reflow cycles. |
For millimeter-wave applications where signal margins are tight, Immersion Silver and OSP remain the industry standard choices to prevent the high conductor losses associated with nickel-bearing finishes.
Fabrication Tolerances That Dictate RF Performance: What to Specify for Your PCB Maker
A design that simulates accurately in an EDA environment can fail in real-world testing if fabrication tolerances are not clearly communicated and tightly controlled.
Etch Factor and Conductor Geometry Tolerances
Chemical etching naturally removes copper laterally as it penetrates down through the foil, resulting in a trapezoidal rather than a rectangular trace cross-section.
The Problem: A trace designed for 50 $\Omega$ with vertical sidewalls will shift in impedance if lateral over-etching reduces trace width ($W$) or modifies the coplanar gap ($S$). A 10% shift in trace width can alter characteristic impedance by several ohms, degrading return loss across the operating band.
Fabrication Specification: Specify trace width tolerances of $\pm 10\ \mu\text{m}$ or better (down to $\pm 12.5\ \mu\text{m}$ depending on starting copper weight). Require the board fabricator to compensate for etch undercut during CAM tooling, and reference trace width targets to the baseline of the trapezoid.
| Conductor Cross-Section Attribute | Ideal Design State | Actual Etched Production State | Impact on mmWave Signal Integrity |
| Geometry Profile | Perfect rectangular cross-section | Trapezoidal cross-section due to lateral chemical undercut | Shifts calculated capacitance and inductance per unit length |
| Top Conductor Width ($W_{\text{top}}$) | Equal to nominal CAD width ($W$) | Narrower than CAD width due to prolonged etchant exposure | Increases localized series resistance; raises characteristic impedance ($Z_0$) |
| Base Conductor Width ($W_{\text{base}}$) | Equal to nominal CAD width ($W$) | Wider than top width; closer to nominal CAD dimension | Defines physical footprint on laminate; alters coplanar ground gap spacing |
| Sidewall Angle (Etch Factor) | $90^\circ$ vertical sidewalls | Tapered sidewalls ($65^\circ – 75^\circ$ typical) | Distorts high-frequency fringing fields in GCPW layouts |
| Engineering CAM Compensation | Uncompensated CAD output | Etch compensation added to CAD line width prior to imaging | Restores effective cross-sectional area to achieve target $Z_0 \pm 5\%$ |
Dielectric Thickness and Registration Control
Variations in prepreg thickness during press lamination alter the distance ($H$) between the RF trace and its ground reference, shifting the system’s characteristic impedance.
Specify controlled dielectric thickness tolerances (typically $\pm 7\%$ to $\pm 10\%$, depending on layer count and core selection).
For differential pairs and GCPW layouts, tight optical layer-to-layer registration is required to ensure signal lines maintain continuous, unperturbed ground clearance throughout all routing transitions.
Ensure clear documentation of high-frequency fabrication notes when placing orders for specialized high speed PCB projects, including target coupon verification and cross-section requirements.
Key Takeaways
Loss Mechanisms: Insertion loss at high frequencies is governed by both dielectric dissipation (Df) and conductor skin-effect losses exacerbated by copper surface roughness. Return loss is driven by impedance mismatches from geometric discontinuities.
Material Selection: High-frequency applications benefit from ceramic-filled hydrocarbon or PTFE laminates that provide low, stable Dk values and Df ratings below $0.004$.
Hybrid Multilayer Stacks: Combining high-frequency cores for outer RF paths with standard glass-epoxy internal cores balances electrical performance with mechanical reliability and cost.
Surface Finishes Matter: Avoid nickel-bearing finishes like ENIG on critical mmWave transmission lines due to high resistive and ferromagnetic losses; favor Immersion Silver or OSP.
Fabrication Control: Tightly communicate etch-factor compensation, dielectric thickness tolerances, and via-stub elimination requirements (such as backdrilling or microvias) in manufacturing documentation.
Technical FAQ
What is an acceptable insertion loss level for 5G mmWave circuits?
Acceptable insertion loss is defined by the overall system link budget. In typical 24 GHz to 40 GHz applications, engineers often target total transmission line losses below $0.5\text{ dB to }1.0\text{ dB per inch}$, depending on line length, available power amplifier output, and receiver sensitivity constraints.
Can standard FR-4 be combined with Rogers materials in a single multilayer board?
Yes. This is referred to as a hybrid multilayer PCB. In these configurations, low-loss laminate cores (such as Rogers RO4003C or RO4350B) are placed on the exterior layers for RF routing, while standard FR-4 materials are used for inner digital and power planes. This configuration requires compatible lamination temperature cycles and balanced resin content to prevent board warpage.
How does copper foil roughness (STD, VLP, HVLP) impact conductor losses at 28 GHz?
Because the skin depth at 28 GHz is under $0.4\ \mu\text{m}$, standard electrodeposited (STD) copper foil creates substantial micro-level surface friction, increasing conductor attenuation. Using Very Low Profile (VLP) or Hyper Very Low Profile (HVLP) foils keeps profile tooth heights close to or below the skin depth, reducing high-frequency conductor loss by up to 30% or more compared to standard foil.
Why does return loss spike at connector transitions, and how can it be avoided?
Return loss spikes at connector interfaces because transition footprints introduce sudden changes in trace width, parasitic pin capacitance, or gaps in the underlying ground reference plane. These reflections can be mitigated by performing three-dimensional electromagnetic (3D EM) field simulations on the connector transition, removing unused inner-layer copper pads, and maintaining continuous ground-via stitching around the RF launch pad.
