Electrical signals in a printed circuit board do not travel at the speed of light in a vacuum (3.0 × 10⁸ m/s or approximately 11.8 inches/ns). Instead, electromagnetic waves move through standard PCB dielectric materials at roughly 45% to 65% of vacuum light speed, translating to a propagation delay of roughly 140 to 180 picoseconds per inch (ps/in) depending on the substrate and trace geometry.

For hardware and layout engineers designing multi-gigabit interfaces such as DDR4/DDR5, PCIe, or high-speed SerDes buses, even minor miscalculations in signal velocity introduce timing skew and narrow eye margins. Three factors govern actual signal speed on a board: the relative dielectric constant (D_k) of the laminate, whether the trace is routed as an outer-layer microstrip or an inner-layer stripline, and fabrication variables such as resin content and glass weave style. This guide covers the governing formulas for velocity of propagation and propagation delay, explains why traces on different layers transmit signals at different speeds, and provides practical layout and fabrication rules to keep timing budgets aligned with physical reality.

Velocity of Propagation (V_p) vs. Propagation Delay (t_pd): Core Formulas

Velocity of propagation (V_p) and propagation delay (t_pd) describe the same physical phenomenon from inverse perspectives. Velocity of propagation measures the distance an electromagnetic wave travels per unit of time, while propagation delay—also called time of flight—measures the time required for a signal to traverse a fixed unit of trace length.

In a non-magnetic dielectric medium, the velocity of propagation is inversely proportional to the square root of the effective relative dielectric constant (D_k,eff or ε_r,eff):

Where:

V_p = Velocity of propagation (m/s or in/ns)

c = Speed of light in a vacuum (≈ 2.998 × 10⁸ m/s or 11.803 in/ns)

D_k,eff = Effective relative dielectric constant of the medium surrounding the trace

Because PCB layout engineers work with physical trace lengths in inches or millimeters and timing budgets in picoseconds, propagation delay (t_pd) is the preferred metric during routing:

Using imperial engineering units where 1 / c ≈ 84.72 ps/in, the practical engineering formula becomes:

For metric calculations where 1 / c ≈ 3.336 ps/mm:

Note: Actual D_k,eff depends on laminate resin-to-glass ratio, signal frequency, and solder mask thickness.

Microstrip vs. Stripline: Why Trace Layer Changes Signal Speed

On the same circuit board built from the same laminate family, signals routed on outer layers travel faster than signals routed on inner layers. This difference occurs because electromagnetic fields propagate through different surrounding media depending on the trace geometry.

An inner-layer stripline trace is completely embedded between two reference planes and surrounded on all sides by resin and glass fiber. Because the electromagnetic field lines remain fully contained within the dielectric substrate, the effective dielectric constant (D_k,eff) equals the bulk dielectric constant (D_k) of the surrounding core and prepreg layers.

An outer-layer microstrip trace sits above a single reference plane while its top and sides are exposed to air (D_k ≈ 1.0) and a thin coating of solder mask (D_k ≈ 3.3 to 3.8). Because a portion of the electric field travels through air above the trace, the combined effective dielectric constant (D_k,eff) is substantially lower than the bulk D_k of the underlying substrate—typically falling between 2.8 and 3.4 for standard FR-4 microstrips.

This velocity mismatch creates a common failure mode when engineers apply simple geometric length matching across mixed layers. If two traces in a synchronous bus are both routed to an identical physical length of 5.0 inches, but Trace A runs on an outer microstrip (145 ps/in) while Trace B runs on an inner stripline (175 ps/in), Trace B arrives 150 ps later than Trace A despite having zero length mismatch. When planning a multi-layer  High Speed PCB stackup, keeping matched signal groups on identical layer types—or compensating in picoseconds rather than millimeters—prevents layer-induced timing skew.

How Laminate Materials and Manufacturing Tolerances Affect Timing

Calculating propagation delay from a nominal datasheet D_k value provides a starting estimate, but finished board performance depends on material behavior across frequency and physical variations introduced during lamination.

Dielectric Dispersion Across Frequency

Standard epoxy-glass FR-4 exhibits noticeable dielectric dispersion: its D_k decreases gradually as signal frequency increases from megahertz into multi-gigahertz ranges. Because digital square waves consist of a fundamental frequency plus multiple odd harmonics, higher-frequency harmonics travel slightly faster than lower-frequency components. Over long traces, this frequency-dependent velocity variation causes phase distortion and edge degradation. Low-loss high-speed laminates maintain a flatter D_k curve across wide frequency bands, keeping propagation delay predictable across harmonics.

Resin Content and Pressed Dielectric Thickness

Prepreg layers consist of woven fiberglass impregnated with uncured resin. During high-temperature lamination pressing, resin flows to fill copper gaps around etched traces. Because glass fibers have a higher dielectric constant (D_k ≈ 6.0 to 6.5) than epoxy or hydrocarbon resins (D_k ≈ 2.5 to 3.5), a higher resin-to-glass ratio lowers the composite D_k and increases signal velocity. Variations in copper density across the panel or deviations in pressed thickness directly alter the local D_k,eff and shift actual propagation delay away from initial field-solver estimates.

The Fiber Weave Effect and Intra-Pair Skew

Woven fiberglass cloth is not electrically uniform at microscopic scales. A differential trace routed directly parallel to the glass yarn bundles may sit over a dense glass bundle (D_k ≈ 6.0), while its complementary trace just a few mils away sits over a resin-rich window (D_k ≈ 3.0). Because the two legs experience different local dielectric constants, one signal travels faster than the other, creating intra-pair skew that converts differential energy into common-mode noise and closes the receiver eye diagram.

Practical Engineering Checklist: Controlling Propagation Delay in Layout and Fabrication

Translating propagation delay calculations into reliable hardware requires coordinated rules inside the EDA tool and explicit documentation in the fabrication package.

Layout and Constraint Setup

• Switch from Length Matching to Delay Matching: For high-speed interfaces that transition between outer and inner layers, configure EDA constraint managers to match total propagation time (in picoseconds) using layer-specific t_pd values rather than raw physical trace length.
• Include Via Flight Time in Budgets: Each layer transition through a plated through-hole via adds roughly 10 to 20 ps of delay depending on board thickness and anti-pad capacitance. Group matched nets so they share identical via counts and layer transitions.
• Isolate Clock and Strobe Reference Environments: Route source-synchronous clock or strobe lines (such as DDR DQS) on the exact same internal layer and with identical spacing rules as their associated data lines to ensure common-mode tracking across temperature and manufacturing tolerances.
• Mitigate Glass Weave Skew Early: For differential pairs operating above 5 Gbps, specify spread-glass prepreg constructions or apply a 10^ panel rotation / shallow zig-zag trace geometry so both conductors average identical resin-to-glass exposure.

Stackup and Fabrication Specification

• Define Stackup by Material Grade and Prepreg Style: Avoid leaving dielectric build-up open to generic substitution. Document the target laminate family, specific prepreg weave styles, and pressed dielectric thicknesses in the fabrication notes.
• Specify Controlled Impedance and D_k Expectations: Because characteristic impedance (Z₀) and propagation delay (t_pd) are both governed by dielectric permittivity and geometry, verifying stackup calculations with your fabricator before routing ensures both targets are met simultaneously. Confirming your stackup against  high speed PCB fabrication capabilities early in layout prevents late-stage serpentine retuning.

Key Takeaways

• Sub-Light-Speed Propagation: Signals in PCB traces travel at roughly 45% to 65% of vacuum light speed, producing typical propagation delays of 140–155 ps/in for microstrips and 170–180 ps/in for striplines on standard FR-4.
• Layer Geometry Alters Velocity: Outer-layer microstrips propagate faster than inner-layer striplines because surrounding air lowers the effective dielectric constant (D_k,eff).
• Time-of-Flight Beats Physical Length: Matching physical trace lengths across mixed layers introduces timing skew; timing-critical buses must be matched by total picosecond delay or confined to identical layer types.
• Fabrication Variables Matter: Prepreg resin content, solder mask thickness, and glass weave alignment directly alter actual propagation delay and must be controlled through explicit stackup specifications.