In high-speed PCB layouts operating at 25 Gbps, 56 Gbps, and 112 Gbps PAM4, plated through-hole (PTH) via stubs act as open-circuit transmission lines that produce destructive signal reflections, severe insertion loss dips, and channel closure. Eliminating these electrical discontinuities requires controlled-depth counterboring, commonly known as backdrilling. For hardware and signal integrity engineers, achieving an acceptable channel eye diagram requires balancing via stub resonant frequency limits against fabrication tolerances, Z-axis drill accuracy, and stackup constraints.

This guide analyzes the physical mechanisms behind via stub resonance in multi-gigabit serializer/deserializer (SerDes) channels, details the mechanical execution of backdrilling, establishes practical tolerance benchmarks, and provides design for manufacturability (DFM) rules for routing, layer assignment, and fabrication documentation.

The Physics of Signal Degradation: Why Via Stubs Become Fatal at 25G+ SerDes

A via stub is the unused portion of a plated through-hole barrel that extends beyond the internal layers where the active signal trace enters and exits. In low-speed digital designs (under 1 to 3 Gbps), this unused copper introduces a negligible capacitive load that rarely disrupts signal transmission.

As channel data rates transition to 28 Gbps NRZ and 56G/112G PAM4, the transition time (rise/fall time) drops into the picosecond domain. Under these conditions, the physical length of even a modest via stub becomes comparable to a significant fraction of the signal’s operational wavelength ($\lambda$).

When an electrical wavefront traverses the active barrel, a portion of the energy branches into the open stub. The energy travels down the stub, reflects off the open-circuit boundary at the bottom, and returns to the main transmission path out of phase. This mechanism produces:

Severe Insertion Loss ($S_{21}$) Notches: Phase cancellation at specific frequencies absorbs power from the main signal line, dropping signal energy sharply across narrow frequency bands.

Return Loss ($S_{11}$) Spikes: Impedance mismatch and phase-shifted reflections create high reflected power back toward the transmitter.

Deterministic Jitter and Intersymbol Interference (ISI): Reflected waveforms linger within the via barrel across unit intervals, causing signal smearing, severe duty-cycle distortion, and horizontal jitter.

Eye-Diagram Collapse: In PAM4 architectures where the available eye height is already reduced to one-third of an NRZ signal for the same voltage swing, the added attenuation from an untreated stub completely closes both upper and lower eye openings.

Addressing these issues in advanced designs demands tight coordination with specialized high-speed PCB manufacturing capabilities capable of sub-mil registration accuracy.

Quarter-Wavelength Resonance: How Unused Barrel Copper Destroys S-Parameters

The primary hazard of an unused via stub is quarter-wavelength ($\lambda/4$) resonance. An open-ended stub functions as a resonant stub filter, transforming the open circuit at its tip into a virtual short circuit at the main junction point whenever the stub length equals one-fourth of the signal’s propagating wavelength.

The fundamental resonant frequency ($f_0$) at which this null occurs can be estimated using the physical stub length and the relative dielectric constant of the surrounding medium:

$$f_0 \approx \frac{c}{4 L \sqrt{D_k}}$$

Where:

$c$ is the speed of light in vacuum ($\approx 3 \times 10^8\text{ m/s}$)

$L$ is the physical length of the via stub (converted to meters)

$D_k$ is the effective relative permittivity (dielectric constant) of the laminate system

Theoretical Resonant Frequencies vs. Stub Length ($D_k \approx 3.6$)

The following table demonstrates how quickly the resonance dip shifts down into critical operational frequencies as stub length increases:

For a SerDes channel to maintain compliance, the fundamental resonant null must remain well above the Nyquist frequency ($f_{\text{Nyquist}} = \text{Data Rate} / 2$ for NRZ; $\text{Data Rate} / 4$ for PAM4) and its primary harmonic components (typically evaluated up to at least $3\times$ the Nyquist frequency to capture edge energy). If an 80-mil stub on a thick backplane resonates near 20 GHz, a 28 Gbps NRZ link ($f_{\text{Nyquist}} = 14\text{ GHz}$) will exhibit substantial attenuation and eye closure due to harmonic attenuation.

Controlled Depth Drilling: The Mechanical Process of Eliminating Via Stubs

Controlled depth drilling—universally termed backdrilling—is a post-plating mechanical machining process that removes unused portions of the conductive copper barrel.

Utilizing reliable controlled-depth drilling and backdrilling services ensures that the cutter stops within the specified dielectric window without severing internal trace connections.

The Zero-Stub Myth: Understanding Manufacturing Tolerances and Critical Stub Limits

A frequent misconception in high-speed design is the assumption that backdrilling completely removes the via stub down to the exact edge of the destination trace. In real-world fabrication, achieving a “zero-mil stub” is physically impossible with mechanical drill spindles.

Why Mechanical Tolerances Prevent Zero Stubs

Machine Z-Axis Runout: Modern CNC drilling spindles feature dynamic depth repeatability of approximately $\pm 1.0\text{ mil}$ to $\pm 1.5\text{ mils}$ ($\pm 0.025\text{ mm}$ to $\pm 0.038\text{ mm}$).

Laminate Thickness Variations: Standard glass-epoxy dielectric materials (such as Megtron 6, Rogers RO4000 series, or high-$T_g$ FR-4) exhibit panel-wide thickness tolerances of $\pm 5\%$ to $\pm 10\%$ due to resin flow variations during lamination.

Drill Bit Wear and Thermal Expansion: High-speed rotation generates local thermal expansion in the spindle and drill flutes, slightly altering effective cutting depth over long production runs.

To ensure the drill tip never cuts into the active signal layer or penetrates the reference ground planes directly shielding the signal, fabricators require an intentional buffer zone known as the Must-Not-Cut Layer clearance. Consequently, a tiny portion of the stub remains after machining.

Backdrilling Capability and Tolerance Matrix

(Note: Exact values depend on material resin content, total layer count, and overall board thickness; specific limits should be confirmed with the engineering team prior to layout finalization).

Stackup Planning and DFM Rules: Designing for Yield and Cost Efficiency

Careful stackup planning reduces manufacturing risk, limits the required number of drill passes, and preserves structural integrity.

1. Optimize Layer Assignments to Minimize Counterbore Depth

Whenever high-speed differential pairs must traverse the board, route the active signals on internal layers as close to the opposite side of the board as possible.

Routing from Layer 1 to Layer 2 leaves almost the entire board thickness as an unneeded stub, requiring a deep, high-aspect-ratio backdrill pass.

Routing from Layer 1 to the second-to-last layer leaves only a nominal stub that may fall within acceptable margins without backdrilling, or requires only a shallow, low-risk backdrill pass.

2. Group High-Speed Nets to Share Target Layer Depths

PCB drilling cycles are billed per tool pass. If high-speed nets exit on Layer 6, Layer 10, Layer 14, and Layer 18, the drill machine must execute four separate depth calibrations and spindle passes per side. Aligning critical high-speed routing to exit on common designated layers allows multiple nets to be processed in a single backdrill operation, significantly lowering production costs and cycle time.

3. Maintain Generous Anti-Pad Clearances on Non-Functional Layers

Because backdrilling employs an oversized tool bit, any plane layers or adjacent internal traces passing near the counterbore radius risk exposure or shorting if anti-pads are sized for standard through-holes.

Increase anti-pad diameters on all layers through which the backdrill cutter will pass by at least $+10\text{ mils}$ over the backdrill tool diameter.

Ensure adjacent signal traces maintain at least 8 to 10 mils of clearance from the outer edge of the backdrill hole envelope.

How to Specify Backdrilling in Manufacturing Files: A Procurement Checklist

Ambiguous fabrication notes remain a leading cause of engineering holds and scrap in high-speed manufacturing. When submitting files for production, follow this verification checklist:

[ ] Dedicated Drill Files: Provide separate, clearly named NC drill files for each backdrill depth (e.g., DRILL_BD_TOP_TO_L04.DRL, DRILL_BD_BOT_TO_L16.DRL). Never merge backdrill hits into the primary through-hole drill file.

Explicit Layer-Pair Definition: Clearly define the starting outer reference layer and the termination target layer in both the drill chart and the fab drawing.

Maximum Allowable Stub Specification: State the absolute maximum acceptable remaining stub length ($L_{\text{max}}$) rather than specifying drill depth directly. For example: “Remaining via stub on nets marked BACKDRILL shall not exceed 6 mils (0.15 mm) inclusive of all fabrication tolerances.”

Must-Not-Cut Layer Identification: Explicitly state the layers that the drill tip must never breach (e.g., “Must-Not-Cut Layer: Layer 5”).

Cross-Sectional Coupon Requests: Specify standard test coupons on panel margins (such as IPC-2221 test coupons) to enable microsection inspection of actual remaining stub lengths and plating retention.

Key Takeaways

High-Speed Impairment: At frequencies corresponding to 25 Gbps+ data rates, via stubs act as quarter-wavelength resonant transmission lines that produce deep notches in insertion loss ($S_{21}$), elevate deterministic jitter, and collapse PAM4 eye diagrams.

Mechanical Solution: Backdrilling uses controlled-depth, oversized drill bits to mechanically sever the conductive copper barrel down to the active routing layer.

Tolerance Reality: Due to machine runout and substrate thickness variations, zero-mil stubs are unachievable in high-volume production. Standard advanced capabilities yield remaining stubs between 4 to 8 mils.

DFM Efficiency: Grouping high-speed traces onto common exit layers minimizes the number of required CNC Z-axis passes, reducing fabrication complexity and unit cost.

File Clarity: Fabrication documentation must explicitly declare layer pairs, maximum permitted stub lengths, and “Must-Not-Cut” layers in dedicated drill tables.

Frequently Asked Questions (FAQ)

What is the maximum acceptable via stub length for a 28 Gbps SerDes channel?

In a typical high-speed channel utilizing 28 Gbps NRZ signaling, the maximum allowable remaining via stub length is generally between 8 and 10 mils ($0.20\text{ mm}$ to $0.25\text{ mm}$). Beyond 10 mils, the quarter-wavelength resonant frequency approaches the third harmonic of the Nyquist frequency, causing noticeable insertion loss degradation and jitter. For 56G and 112G PAM4 designs, stubs should ideally be limited to $\le 4\text{ to } 6\text{ mils}$ ($0.10\text{ to } 0.15\text{ mm}$).

Does backdrilling impact impedance continuity in the remaining via barrel?

Removing the stub alters the total capacitive loading of the via. While backdrilling removes the excess capacitance introduced by the unused barrel, it leaves an air cavity or dielectric-filled void in place of the copper. High-speed designers must model the backdrilled via geometry in a 3D electromagnetic field solver (such as Ansys HFSS or CST) to adjust the via pad diameter and anti-pad clearance, ensuring the remaining barrel maintains the target single-ended (50 $\Omega$) or differential (85–100 $\Omega$) impedance.

How much does backdrilling typically increase PCB manufacturing costs?

Backdrilling typically increases bare-board fabrication costs by approximately 10% to 25%, depending on the overall layer count, panel thickness, and the number of independent backdrill passes required per side. Designing layouts to minimize the number of unique target depths directly constrains these processing surcharges.

Can both the top and bottom sides of the same PCB be backdrilled?

Yes. Dual-sided backdrilling is routinely performed on thick, high-layer-count multi-layer boards (e.g., network switches, server motherboards, and test equipment backplanes). In this configuration, signals routed between mid-stackup internal layers have their stubs removed from both the top and bottom surfaces in separate manufacturing operations.