A SerDes (Serializer/Deserializer) lane is an integrated physical link that converts wide, parallel digital data from an on-chip bus into high-speed serial bitstreams for transmission over a single differential pair, then reconstructs parallel data at the receiver. In high-speed PCB systems operating above 10 Gbps—such as PCIe Gen 5/6, 100G/400G Ethernet, and AI accelerator clusters—SerDes architectures eliminate the pin-count bottlenecks and inter-line skew limits of legacy parallel buses. However, at multi-gigabit rates, the physical printed circuit board stops behaving as an ideal conductor and becomes an active, frequency-dependent transmission channel.
Selecting the right dielectric substrates, controlling copper surface roughness, managing via stubs through backdrilling, and maintaining strict trace impedance determine whether a SerDes link achieves an acceptable Bit Error Rate (BER) or suffers complete eye-diagram closure. This guide examines how SerDes architectures function, how signaling shifts from NRZ to PAM4 impact noise margins, and the specific layout and fabrication parameters required for successful high-speed PCB implementation.
The Evolution of Interconnects: What Is a SerDes Lane?
A SerDes lane consists of a transmitter (Tx) that serializes parallel data, a transmission channel (traces, vias, connectors, and cables), and a receiver (Rx) that samples the bitstream and deserializes it back into parallel words. It operates using point-to-point differential signaling, embedding clock timing directly into the data payload to remove the need for dedicated physical clock traces.
| Stage | Subsystem | Primary Function & Physical Implementation |
|---|---|---|
| Source | Transmitter (Tx) | Parallel-to-serial conversion, PLL clock synthesis, and feed-forward equalization |
| Medium | Differential Channel | Physical signal transmission via PCB stripline/microstrip, vias, and connectors |
| Destination | Receiver (Rx) | Serial-to-parallel conversion, CTLE/DFE equalization, and clock/data recovery (CDR) |
Historically, digital hardware relied on wide parallel buses (such as PCI, ATA, and early memory buses) to scale bandwidth. As clock frequencies climbed past a few hundred megahertz, parallel buses encountered insurmountable physical limits:
Trace Skew Across Wide Busses: Minor physical length variations between 32 or 64 parallel lines caused bits transmitted in the same clock cycle to arrive out of sync.
I/O Routing Congestion: Routing dozens of synchronized traces consumed substantial board surface area and congested BGA escape fields.
Simultaneous Switching Noise (SSN): Switching dozens of single-ended lines at once induced severe ground bounce and power rail ripple.
By consolidating high-throughput data streams into serialized differential pairs, SerDes links dramatically shrink routing footprints while allowing per-lane data rates to reach 28 Gbps, 56 Gbps, 112 Gbps, and higher.
Parallel Bus vs. High-Speed SerDes Architecture
| Feature | Legacy Parallel Bus | High-Speed SerDes Lane |
|---|---|---|
| Physical Interconnect | Multi-conductor single-ended lines (32/64 bits) | Single differential pair (Tx+, Tx- / Rx+, Rx-) |
| Clock Architecture | Separate source-synchronous clock trace | Clock embedded in data stream via encoding |
| Trace Skew Impact | Severe inter-bit timing skew limits line length | Eliminated across lanes; only intra-pair skew matters |
| PCB Real Estate | High routing area; dense pin escape requirements | Compact routing; standard microstrip/stripline pairs |
| Noise Immunity | Sensitive to crosstalk and return-path discontinuities | High common-mode rejection ratio (CMRR) |
| Maximum Per-Line Rate | Typically constrained below 1 Gbps | Scalable from 10 Gbps to 112 Gbps+ per physical lane |
Inside the SerDes Architecture: Key Functional Blocks Across the Channel
A complete SerDes channel is a closed-loop system encompassing silicon-level analog front ends and the passive PCB interconnect between them.
| Step | Functional Block | Domain | Operational Role in the Link |
|---|---|---|---|
| 1 | Parallel Data In | Silicon (Tx Core) | Wide digital word input from internal system logic (e.g., 32-bit/64-bit bus) |
| 2 | Shift Register / Serializer | Silicon (Tx) | Converts parallel data words into a single sequential, high-speed bitstream |
| 3 | PLL & Tx Equalizer (FFE) | Silicon (Tx) | Synthesizes baud-rate clock; applies pre-emphasis to counteract channel loss |
| 4 | PCB Traces, Vias & Connectors | Passive Interconnect | Transmits differential signals across board substrates and layer transitions |
| 5 | CTLE (Analog Filter) | Silicon (Rx) | High-pass linear filtering to restore high-frequency signal attenuation |
| 6 | CDR & DFE Equalizer | Silicon (Rx) | Reconstructs sampling clock; subtracts post-cursor inter-symbol interference |
| 7 | Deserializer / Framer | Silicon (Rx) | Reconstructs synchronized parallel data words for downstream logic |
Transmitter Path (Tx): Serialization, PLL Clock Synthesis, and FFE
Clock Synthesis (PLL)
An on-chip Phase-Locked Loop multiplies a low-frequency reference clock up to the target multi-gigahertz baud rate to clock out individual bits.
Serializer
High-speed multiplexers and shift registers convert parallel digital words (e.g., 32-bit or 64-bit wide buses running at a fraction of the clock speed) into a continuous, sequential bitstream.
Feed-Forward Equalization (FFE)
High-frequency signal components attenuate faster than low-frequency components as signals travel down copper traces. Tx FFE applies pre-emphasis or de-emphasis—boosting high-frequency transitions or attenuating static low-frequency runs—to compensate for channel loss before the signal enters the PCB.
The Physical Interconnect Channel
The physical channel represents the entirely passive portion of the link. It includes the transmitter package substrate, BGA escape balls, PCB microstrips or striplines, through-hole or blind vias, AC coupling capacitors, board-to-board connectors, and receiver package leads. In high-speed PCB layouts, every geometry change along this path introduces impedance mismatches, signal reflections, and dielectric absorption.
Receiver Path (Rx): CTLE, DFE, and CDR
Continuous Time Linear Equalization (CTLE)
An active analog high-pass filter within the receiver that attenuates low frequencies and amplifies high frequencies near the Nyquist point to reopen a collapsed eye diagram.
Decision Feedback Equalizer (DFE)
A non-linear equalizer that samples previously resolved bits and subtracts their residual post-cursor Inter-Symbol Interference (ISI) without boosting high-frequency channel noise.
Clock and Data Recovery (CDR)
Because high-speed SerDes channels do not carry a separate clock line, the CDR extracts phase and timing directly from signal edges to sample incoming symbols accurately at center-eye.
Encoding Schemes: Why the Transition from NRZ to PAM4 Changes Everything
To increase data throughput, system architectures historically raised the clock frequency. However, channel attenuation on standard circuit boards escalates rapidly with frequency. To overcome this physical brick wall, advanced interconnect standards transitioned from binary Non-Return-to-Zero (NRZ) to four-level Pulse Amplitude Modulation (PAM4).
| Signaling Mode | Voltage Level | Logic State | Symbol Capacity | Eye Pattern Output |
|---|---|---|---|---|
| NRZ | Level 1 (High) / Level 0 (Low) | 0 / 1 | 1 bit / UI | 1 large eye opening with maximum vertical noise margin |
| PAM4 | Level 3 (Full) / Level 2 (2/3) / Level 1 (1/3) / Level 0 (Zero) | 11 / 10 / 01 / 00 | 2 bits / UI | 3 vertically stacked, compressed eye openings (~33% height each) |
Signal Representation and Nyquist Frequency
NRZ: Uses two discrete voltage levels to represent one bit per unit interval (UI). Transmitting a 56 Gbps stream requires a symbol rate of 56 GBaud, placing the fundamental Nyquist frequency at 28 GHz.
PAM4: Uses four discrete voltage levels (00, 01, 10, 11) to encode two bits per symbol. Transmitting a 56 Gbps stream requires only 28 GBaud, dropping the Nyquist frequency to 14 GHz.
Halving the Nyquist frequency significantly reduces frequency-dependent dielectric and conductor losses over standard transmission lines.
The Trade-Off: SNR Penalty and Noise Margin
While PAM4 eases insertion loss by operating at half the frequency for a given data rate, it creates significant physical design challenges:
Signal-to-Noise Ratio (SNR) Drop: With the full signal voltage swing split into three eye openings instead of one, the vertical eye height of each PAM4 eye is one-third (33%) of an NRZ eye. This equates to an immediate physical SNR penalty of approximately -9.54 dB.
Sensitivity to Reflection and Crosstalk: Because the voltage separation between adjacent logic states is substantially smaller, minute reflections from via stubs, BGA pad discontinuities, or trace-to-trace crosstalk that would not harm an NRZ link can completely close a PAM4 eye.
NRZ vs. PAM4 Technical Comparison
| Metric | NRZ (Non-Return-to-Zero) | PAM4 (Pulse Amplitude Modulation 4-Level) |
|---|---|---|
| Bits Per Symbol (UI) | 1 bit | 2 bits |
| Voltage Levels | 2 levels (High, Low) | 4 levels (0, 1/3, 2/3, Full) |
| Eye Openings | 1 large eye | 3 smaller, vertically stacked eyes |
| Nyquist Frequency (at 56 Gbps) | 28 GHz | 14 GHz |
| Inherent SNR Loss | 0 dB baseline | ~ -9.54 dB reduction |
| PCB Tolerance Sensitivity | Moderate; tolerant of minor impedance steps | Extreme; demands tight impedance and trace tolerances |
| Typical Target Applications | PCIe Gen 3/4, 10G/25G Ethernet | PCIe Gen 6, 56G/112G/224G Ethernet, AI Fabrics |
The Channel Bottleneck: Why PCB Designers Hold the Key to SerDes Success
Modern SerDes transmitters and receivers integrate sophisticated DSP, FFE, and DFE equalizers, but their ability to reconstruct signals is finite. Equalization cannot recover bits lost to severe reflection notches, phase cancellation, or excessive dielectric attenuation. The physical board layout ultimately dictates the channel’s operational budget.
| Physical Mechanism | Root Cause in PCB Substrate | Impact on Differential Signal Integrity |
|---|---|---|
| Skin Effect Resistance | High-frequency current crowds into thin outer copper edges | Increases conductor loss; severely attenuated by rough foil profiles |
| Dielectric Absorption | Dipole relaxation in core resin at multi-GHz frequencies | Drives frequency-dependent insertion loss proportional to material Df |
| Fiber Weave Skew | Differential legs travel over uneven glass yarn vs. resin pockets | Creates propagation velocity mismatch, intra-pair skew, and mode conversion |
| Via Stub Resonance | Unused plated via barrel functions as an open quarter-wave stub | Produces a sharp resonant notch filter, nulling out critical Nyquist harmonics |
Insertion Loss & Dielectric Absorption (Skin Effect and Df/Dk)
Total channel insertion loss stems from two primary mechanisms:
Conductor Loss
As signal frequency rises, alternating current crowds toward the outer periphery of the copper trace (the skin effect). At 28 GHz, the skin depth of copper is well under 0.5 microns. If the copper surface profile (roughness) is comparable to or larger than the skin depth, the effective path length increases, dramatically driving up resistive loss.
Dielectric Loss
The insulating resin and fiberglass absorb electromagnetic energy as molecular dipoles reorient at multi-gigahertz rates. This loss is directly proportional to the material’s Dissipation Factor (Df or loss tangent) and operating frequency.
Return Loss and Impedance Discontinuities
Any geometric shift along a differential pair—such as BGA escape breakouts, surface-mount component pads, layer change vias, or board connectors—alters the trace’s instantaneous characteristic impedance. When an incoming wave strikes an impedance discontinuity, a portion of the energy reflects toward the source (quantified as Return Loss, S11). Reflections travel back and forth, appearing as inter-symbol interference that degrades eye width and height.
Intra-Pair Skew & Fiber Weave Effect
High-speed SerDes signaling relies on differential receivers subtracting the two complementary signals (Vdiff = V_+ – V_-) to cancel common-mode noise. If one leg of the differential pair arrives even a few picoseconds later than the other (intra-pair skew):
The differential signal amplitude drops.
Phase shifts convert differential energy into common-mode noise, driving up electromagnetic radiation (EMI).
In woven PCB substrates, if one trace runs directly over glass yarn bundles while its partner runs over resin-rich pockets, the differences in relative dielectric constant (εr of E-glass is ~6.6; resin is ~3.0) create significant phase skew over moderate trace lengths.
| Routing Path Location | Local Dielectric Constant (εr) | Propagation Speed | System Level Impact |
|---|---|---|---|
| Trace (+) over Glass Bundle | Higher (~6.0 to 6.6) | Slower | Accumulates phase delay relative to complementary trace |
| Trace (-) over Resin Pocket | Lower (~3.0 to 3.5) | Faster | Outpaces complementary trace, inducing severe intra-pair skew |
Via Stubs and the Resonant Frequency Trap
When a signal changes layers through a plated through-hole (PTH) via, the unused portion of the barrel extending past the target internal routing layer forms an open-ended electrical stub.
This stub acts as a quarter-wavelength transmission line resonator. At its resonant frequency:
the stub reflects signals 180^ out of phase, producing a deep null (notch filter) in the channel’s insertion loss (S21) profile. For multi-gigabit links, an untreated via stub as short as 15 to 20 mils can completely attenuate signals near the Nyquist frequency.
Practical Layout Guidelines: Designing Robust SerDes Channels on PCB
Translating SerDes silicon capabilities into reliable hardware requires disciplined routing practices. To support robust signal integrity across high-speed channels, layout teams should apply systematic design and manufacturing constraints:
| Layout Constraint | Recommended Practice | Failure Mode if Violated |
|---|---|---|
| Differential Coupling | Tightly coupled, uniform trace spacing along the entire run | Local impedance shifts and susceptibility to external noise |
| Reference Plane Continuity | Solid, unbroken ground plane directly beneath both traces | Loop inductance surges, severe impedance cliffs, and EMI radiation |
| Layer Transitions | Place dual GND return stitching vias within 20–30 mils of signal vias | High-frequency return path disconnect, increasing crosstalk and jitter |
| Corner Geometry | Smooth 45° mitered bends or rounded curved routing | Excess parasitic capacitance and localized impedance dips |
Differential Impedance Control (85 Ω vs. 100 Ω)
Most SerDes standards specify a target differential impedance:
85 Ω Differential: Common in modern PCI Express (Gen 3 through Gen 6) and select memory architectures to reduce reflections at BGA packages and connectors.
100 Ω Differential: The industry standard for Ethernet, SAS/SATA, and traditional telecommunication interfaces.
Maintain tightly coupled, uniform trace geometries without necking down traces except within dense BGA breakout fields. When geometry must narrow for escape routing, adjust the underlying dielectric spacing or adjacent ground clearance to maintain impedance targets.
Reference Plane Continuity
SerDes differential pairs must route over solid, uninterrupted reference ground planes throughout their entire run.
Never route high-speed differential pairs across splits, slots, or cutouts in power or ground planes. Crossing a plane split forces high-frequency return currents to loop around the void, creating massive loop inductance, impedance spikes, and severe crosstalk.
Prefer routing critical SerDes channels on internal stripline layers (sandwiched between two ground planes) rather than outer microstrip layers to ensure consistent dielectric environments and shield against EMI.
Phase Compensation and Skew Matching
Keep physical length mismatch within a differential pair below ±1 to 2 mils (or under 1 picosecond of propagation delay).
Perform length adjustments close to where any geometric asymmetry occurs (such as bends or package pin escapes) using tight, symmetric serpentine compensation. This prevents phase skew from accumulating over long distances.
Avoid right-angle corners; route bends with smooth 45^ angles or circular arcs to minimize local capacitance.
Ground Return Vias at Layer Transitions
Whenever a differential pair transitions between board layers, its high-frequency return current must follow the signal to the new reference plane.
Place at least two ground stitching vias immediately adjacent to the signal via pair (within 20 to 30 mils center-to-center).
If switching between planes of different potentials, place low-inductance ceramic stitching capacitors directly beside the signal vias to provide an AC return path.
Material Selection and PCB Fabrication Controls for SerDes Channels
Even ideal layout geometry will fail if implemented on standard FR-4 materials or produced with standard manufacturing tolerances. Commercial success relies on collaboration with an experienced PCB manufacturer capable of tight fabrication tolerances and specialized material handling.
High-Speed PCB Routing and Fabrication Guidelines
| Parameter | Recommended Specification | Engineering Justification |
|---|---|---|
| Impedance Tolerance | ± 5% (Standard is ± 10%) | Minimizes boundary reflections and maintains return loss margins in PAM4 links. |
| Intra-Pair Length Skew | ≤ 1 mil (≤ 0.15 ps delay) | Prevents differential-to-common-mode noise conversion and preserves eye opening. |
| Via Stub Length | ≤ 6 to 8 mils (Requires Backdrilling) | Shifts the resonant quarter-wave notch well beyond operating Nyquist frequencies. |
| Fiber Weave Mitigation | Spread glass fabric (e.g., 1067, 1078) or zig-zag/angled routing | Prevents localized dielectric constant shifts between complementary traces. |
| Copper Foil Profile | VLP (Very Low Profile) or HVLP (Rz ≤ 1.5 µm) | Mitigates skin-effect losses at frequencies above 10 GHz. |
| Dielectric Loss Tangent | Df ≤ 0.004 (Ultra-Low-Loss for ≥ 28 Gbps) | Keeps overall channel insertion loss within receiver equalization limits. |
Low-Loss Laminate Selection
Standard FR-4 exhibits a high dissipation factor (Df ≈ 0.015 to 0.020) and dielectric constant instability over frequency, making it unsuitable for SerDes channels running beyond 5 to 10 Gbps over distances greater than a few inches. Advanced high-speed SerDes designs require specialized copper clad laminates:
Mid-Loss Laminates (Df ≈ 0.008 to 0.010): Suitable for shorter 10 Gbps links.
Low-Loss Laminates (Df ≈ 0.004 to 0.007): Standard for PCIe Gen 4/5 enterprise servers.
Ultra-Low-Loss Laminates (Df ≤ 0.002 to 0.003): (e.g., Panasonic Megtron 6/7, Rogers RO4000 series, or equivalent high-frequency systems) Essential for 56 Gbps and 112 Gbps PAM4 architectures to meet stringent channel loss budgets.
Copper Foil Profiles: Standard ED vs. HVLP
At multi-gigahertz frequencies, current flows through the surface micro-contours of the copper foil. Standard electrodeposited (ED) copper features high surface roughness (Rz > 5 µm) to improve mechanical peel strength with the resin, but this roughness causes significant insertion loss penalties.
Specifying Very Low Profile (VLP) or Hyper Very Low Profile (HVLP) copper foil (Rz ≤ 1.0 to 1.5 µm) provides a smoother conduction path, preserving signal amplitude at high Nyquist frequencies.
Precision Backdrilling (Controlled-Depth Counter-Boring)
To prevent via stubs from attenuating signal energy, board fabrics specify controlled-depth drilling (backdrilling). After through-hole plating, a computer-controlled drill bit slightly larger than the via hole drills out the unused copper barrel from the opposite side of the board. High-precision manufacturing controls backdrill residual stubs to under 6 to 8 mils, moving the quarter-wave resonant notch out to frequencies where it cannot disrupt the link.
| Via Processing Method | Cross-Section Configuration | Stub Status | High-Frequency Link Behavior |
|---|---|---|---|
| Standard Plated Through-Hole (PTH) | Full-length conductive copper barrel from Layer 1 to Layer 12 | Retains long unused copper stub below Layer 4 route | Introduces deep quarter-wavelength resonance nulls within target Nyquist band |
| Precision Depth Backdrilling | Controlled-depth oversized drill removes copper from Layer 12 up to Layer 4 | Residual stub minimized to ≤ 6 to 8 mils | Eliminates resonant reflections and shifts notch filter well beyond operating spectrum |
When building mission-critical backplanes, accelerator boards, or network line cards, design teams must coordinate with an engineering-driven manufacturing partner. Fabricators like Mars PCB Innotech provide advanced high-speed PCB fabrication services that maintain rigorous etch compensation, precise laser depth control, and material testing to ensure complex SerDes links achieve target Bit Error Rates out of the gate.
Key Takeaways
- SerDes Overcomes Parallel Limitations: High-speed SerDes architectures eliminate trace skew and routing congestion issues by embedding timing data into high-speed differential bitstreams.
- PAM4 Trades SNR for Bandwidth: While PAM4 halves the Nyquist frequency relative to NRZ for the same data rate, it reduces eye height by two-thirds (-9.54 dB SNR penalty), requiring much tighter physical channel tolerances.
- The Interconnect Is an Active Attenuator: At multi-gigabit rates, PCB traces and vias behave as transmission lines prone to insertion loss, return loss, and resonance. Equalization cannot fix catastrophic channel reflections.
- Via Stubs Require Backdrilling: Unused plated via barrels act as resonant stubs that can cause severe notch filtering at the Nyquist frequency. High-speed channels require backdrilling to keep remaining stubs under 6 to 8 mils.
- Material Selection Dictates Eye Opening: Upgrading from standard FR-4 to low-loss or ultra-low-loss laminates (with low Df) combined with HVLP smooth copper foil is mandatory to preserve signal integrity in 28G+ links.
- Manufacturing Tolerance Matters: Tight impedance control (± 5%) and precise etch factor compensation prevent localized impedance discontinuities that degrade performance.
Frequently Asked Questions
How do I know if my SerDes PCB traces require backdrilling?
Backdrilling is generally required whenever the quarter-wavelength resonant frequency of an unused via stub falls near or below the operating Nyquist frequency of your signal. A reliable engineering rule of thumb is to calculate the stub length: if the stub length exceeds (c / 4 · fNyquist · √εr), it must be backdrilled. In practice, almost all 28 Gbps+ NRZ and 56 Gbps+ PAM4 SerDes channels require backdrilling on all signal vias undergoing layer transitions to keep the remaining stub below 6 to 8 mils.
What is the standard differential impedance for PCIe vs. Ethernet SerDes?
PCI Express standards (PCIe Gen 3, Gen 4, Gen 5, and Gen 6) specify an 85 Ω nominal differential impedance target (± 10% standard, or ± 5% for high-performance channels) to match on-chip termination and connector geometries. Conversely, IEEE Ethernet SerDes standards (such as 10GBASE-KR, 25GBASE-KR, and 100GBASE-CR4) and many optical module interfaces specify a nominal 100 Ω differential impedance. Always verify the transceiver PHY specifications before establishing stackup geometries.
Can SerDes differential pairs be routed across plane splits?
No. High-speed SerDes differential pairs should never be routed across splits, slots, or cutouts in adjacent reference planes. Although differential signals are theoretically self-referencing, high-frequency return currents travel directly on the ground plane directly beneath each trace. A split interrupts this return path, forcing current into wide, inductive loops that cause immediate impedance discontinuities, severe signal distortion, and excessive EMI.
How does the fiber weave effect degrade SerDes links, and how can it be mitigated?
The fiber weave effect occurs because the fiberglass bundles (Dk ~6.0) and resin matrix (Dk ~3.0) within a standard laminate have different dielectric constants. If one trace of a differential pair sits over glass while its partner sits over resin, the signals travel at different phase velocities, creating intra-pair skew that degrades the differential signal and generates common-mode noise. Mitigate this by specifying spread-glass fabrics (such as 1067, 1078, or 3313 styles), angling your routing relative to the board material weave by 10^ to 45^, or rotating the entire PCB design on the production panel.
