Signal attenuation is the gradual loss of electrical signal amplitude as a high-frequency waveform travels from a transmitter to a receiver across a physical interconnect. In a multi-gigabit High Speed PCB, this energy loss—quantified in decibels (dB) as insertion loss (S21)—acts as a low-pass filter that rounds off sharp digital edges, shrinks vertical eye height, and increases bit error rates (BER).
Successfully routing 10G, 25G, 56G, or 112G interfaces depends on three primary factors: the target Nyquist frequency of the data protocol, the electrical properties of the laminate and copper foil, and the physical geometry of the transmission path. Rather than guessing whether a standard FR-4 board can support a given trace length, hardware and signal integrity engineers rely on an end-to-end link loss budget to allocate allowable decibels across packages, connectors, vias, and copper traces before layout begins.
This guide breaks down the physical mechanisms behind signal attenuation, provides a step-by-step framework to calculate a multi-gigabit channel loss budget, and outlines practical engineering trade-offs to keep insertion loss within receiver equalization limits.
What Is Signal Attenuation in Multi-Gigabit PCB Links?
Signal attenuation measures how much signal power is lost between the input port (Port 1) and the output port (Port 2) of a transmission channel. In vector network analyzer (VNA) measurements and channel simulations, this loss is expressed as the forward transmission scattering parameter, S21, measured in negative decibels (for example, -12 dB) or stated as a positive attenuation figure (12 dB of loss).
Because digital bitstreams are composed of a fundamental clock frequency plus odd harmonics, high-frequency components experience far greater attenuation than low-frequency components. When high-frequency harmonics are stripped away, fast rising and falling edges slow down, causing consecutive bits to smear into one another—a phenomenon known as inter-symbol interference (ISI).
| Design Parameter | Legacy Low-Speed Links (< 1 Gbps) | Multi-Gigabit Links (10 Gbps – 112 Gbps) |
|---|---|---|
| Critical Evaluation Frequency | Fundamental clock rate | Nyquist frequency (0.5 × baud rate) and higher harmonics |
| Dominant Loss Mechanism | DC trace resistance (I2R) | Dielectric dissipation (Df) and high-frequency skin effect |
| Laminate Sensitivity | Standard FR-4 is typically sufficient | Requires controlled Dk/Df laminates based on channel length |
| Receiver Recovery | Simple threshold comparator | Requires Tx emphasis and Rx equalization (CTLE, DFE) |
In multi-gigabit architectures, SerDes transceivers specify a maximum allowable channel insertion loss at the Nyquist frequency—the frequency equal to half the symbol rate (for example, 14 GHz for 28 Gbps NRZ or 26.56 GHz for 112 Gbps PAM4, depending on the specific protocol standard). If total channel attenuation exceeds what the receiver’s Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE) can compensate for, the eye diagram closes and reliable data recovery fails.
The Four Primary Sources of Signal Attenuation on a High Speed PCB
Total channel insertion loss on a High Speed PCB is the cumulative result of four distinct physical mechanisms. Separating these sources allows designers to identify whether a budget shortfall is driven by substrate chemistry, copper surface profile, or physical routing discontinuities.
1. Dielectric Loss
Dielectric loss occurs when alternating electric fields cause polar molecules inside the insulating resin and glass weave to oscillate, converting electromagnetic signal energy into heat. Dielectric attenuation increases roughly linearly with frequency and is directly governed by the material’s dissipation factor (Df) and the square root of its dielectric constant (Dk). Standard epoxy-glass laminates exhibit higher Df values that rapidly absorb energy above 5 GHz, whereas low-loss hydrocarbon, polyphenylene ether (PPE), or PTFE-based substrates maintain much lower Df ratings across multi-gigabit bands.
2. Conductor Loss and the Skin Effect
At direct current (DC), electrical current flows uniformly through the entire cross-section of a copper trace. As signal frequency climbs into the gigahertz range, electromagnetic self-inductance forces current toward the outer perimeter of the conductor—a phenomenon called the skin effect. Because current is confined to a thin outer layer (the skin depth, which shrinks inversely with the square root of frequency), the effective cross-sectional area drops and AC resistance rises proportionally to the square root of frequency (√f).
3. Copper Foil Surface Roughness
To ensure strong mechanical peel strength between copper foil and dielectric prepreg during lamination, manufacturers treat the matte side of copper foil with microscopic nodules. At multi-gigabit frequencies, when skin depth shrinks to around one micron or less, current must follow the jagged peaks and valleys of these nodules rather than traveling in a straight line. This extended path length significantly increases effective conductor resistance beyond smooth-conductor theoretical calculations. Selecting low-profile copper foils—such as Very Low Profile (VLP) or Hyper Very Low Profile (HVLP)—directly reduces high-frequency resistive losses in low-loss High Speed PCB fabrication.
4. Impedance Discontinuities, Vias, and Connectors
While dielectric and conductor losses convert signal energy into heat, structural discontinuities reflect energy back toward the transmitter. Every reflection reduces the forward-transmitted energy reaching the receiver, appearing as dips or notches in the S21 insertion loss curve. Common culprits include uncompensated via barrels, unused via stubs acting as quarter-wave resonant filters, reference plane splits, and connector launch pads.
| Attenuation Source | Physical Mechanism | Frequency Scaling | Key Material / Geometry Variables | Primary Engineering Mitigation |
|---|---|---|---|---|
| Dielectric Loss | Molecular polarization and heat dissipation in resin/glass | Approximately linear (∝ f) | Dissipation factor (Df), dielectric constant (Dk) | Upgrade from standard FR-4 to low-Df or ultra-low-Df laminates |
| Conductor Loss (Smooth) | High-frequency current crowding near conductor surface | Proportional to square root (∝ √f) | Trace width, copper conductivity, trace length | Widen signal traces (with thicker dielectric to preserve impedance) |
| Copper Roughness Loss | Current path lengthening over bonding nodules | Accelerates when skin depth ≤ surface roughness (Rz) | Copper foil profile (Standard RTF vs. VLP / HVLP) | Specify VLP or HVLP copper foils on high-speed signal layers |
| Via & Connector Discontinuities | Impedance mismatches and stub resonance reflections | Resonant dips at specific stub quarter-wave frequencies | Via stub length, anti-pad diameter, pad capacitance | Use backdrilling, blind/buried vias, and anti-pad optimization |
Building a Multi-Gigabit Link Loss Budget: A Five-Step Framework
Building a link loss budget translates a chip manufacturer’s transceiver specification into a concrete physical routing rule—specifically, the maximum allowable trace length on the PCB. Follow this five-step engineering workflow before finalizing component placement or stackup layers.
Step 1: Establish the Total Chip-to-Chip Loss Allowance
Consult the SerDes or PHY datasheet (or the governing interface standard such as PCIe, Ethernet, or USB) to determine the maximum supported die-to-die insertion loss at the target Nyquist frequency. Confirm the exact equalization assumptions behind that figure, such as whether the budget assumes active Tx de-emphasis, Rx CTLE, and a specific number of DFE taps.
Step 2: Deduct Transmitter and Receiver Package Losses
Datasheet channel budgets are frequently specified from silicon die bump to silicon die bump, whereas PCB layout occurs from BGA ball to BGA ball. Subtract the insertion loss of both the transmitter IC package and the receiver IC package at the Nyquist frequency using IBIS-AMI models or vendor package loss tables.
Step 3: Subtract Connectors, Cables, and AC Coupling Capacitors
If the link crosses a board-to-board mezzanine connector, backplane header, SFP/QSFP cage, or external cable assembly, deduct the vendor-verified insertion loss for every interconnect component in the path. Include small discrete discontinuities such as DC-blocking capacitors and ESD protection diodes, which introduce localized impedance steps and insertion loss at multi-gigabit speeds.
Step 4: Reserve Engineering Margin for Real-World Variation
Never allocate 100% of the remaining budget to nominal room-temperature trace loss. Reserve a safety margin (typically 10% to 15% of the total channel budget, subject to system reliability targets and vendor guidelines) to account for:
- Elevated operating temperatures inside the enclosure, which increase copper resistivity and dielectric dissipation.
- Relative humidity shifts affecting resin moisture absorption.
- PCB fabrication tolerances in trace etching width, dielectric thickness, and glass-to-resin ratio.
Step 5: Calculate Net PCB Trace Budget and Maximum Trace Length
Subtract all non-trace losses and the design margin from the total chip-to-chip allowance to find the Net PCB Trace Budget. Divide this remaining decibel budget by the per-inch attenuation rate (dB/inch) of your proposed stackup and laminate at the Nyquist frequency to determine the maximum permissible routing distance.
End-to-End Link Loss Budget Allocation Worksheet (Template)
The table below illustrates how a hardware engineer structures a chip-to-chip budget audit. Actual decibel figures must be populated from verified component datasheets, 3D field solver simulations, and laminate supplier data sheets.
| Channel Segment / Budget Item | Loss Contribution at Nyquist Frequency | Determination Method | Engineering Notes |
|---|---|---|---|
| 1. Total Die-to-Die Allowance | +Xtotal dB | SerDes / Protocol Specification | Verify Tx/Rx equalization settings assumed in spec |
| 2. Tx + Rx IC Package Loss | -Xpkg dB | IC Vendor Package Model / Datasheet | Omit if budget is already defined ball-to-ball |
| 3. Connectors & Cable Assemblies | -Xconn dB | Connector Vendor S-Parameter Data | Include mating cycles and worst-case tolerance |
| 4. Signal Vias & AC Capacitors | -Xvia dB | 3D EM Field Solver Simulation | Account for layer transitions and remaining stub length |
| 5. Environmental & Process Margin | -Xmargin dB | System Engineering Guideline | Covers thermal drift, humidity, and etching tolerances |
| 6. Net PCB Trace Budget | = Xnet dB | Remaining Allowable Trace Loss | Must exceed (Trace Length × Material dB/inch) |
Engineering Trade-Offs: Meeting Tight Loss Budgets Without Over-Designing
When preliminary calculations show that planned routing distances exceed the Net PCB Trace Budget, jumping immediately to the lowest-Df PTFE laminate is rarely the most cost-effective decision. High-loss materials increase raw board cost and can introduce stricter lamination press cycles or drilling requirements. Instead, evaluate mitigations in tiers—starting with layout and geometric adjustments before upgrading substrate materials.
| Optimization Tier | Engineering Lever | Effect on Insertion Loss | Stackup & Cost Impact | When to Apply |
|---|---|---|---|---|
| Tier 1: Placement & Geometry | Shorten routing paths via floorplan adjustment | Directly scales total trace loss down proportionally | Zero laminate cost increase; requires early mechanical/layout alignment | Always the first step on any loss-critical interface |
| Tier 1: Placement & Geometry | Widen differential trace width (with thicker dielectric) | Reduces conductor skin-effect loss per inch | Increases board thickness or requires wider trace pitch | Effective when conductor loss dominates short-to-medium traces |
| Tier 2: Via & Structural Control | Backdrill (controlled-depth drill) unused via stubs | Eliminates quarter-wave resonant S21 drop-offs | Adds secondary CNC drilling step; moderate cost increase | Essential for thick backplanes or multi-layer boards above 10 Gbps |
| Tier 2: Via & Structural Control | Route on outer microstrip vs. inner stripline | Microstrip often exhibits slightly lower loss per inch due to air interface | Exposed to EMI and solder mask loss; requires careful reference control | Suitable for short point-to-point links where EMI rules allow |
| Tier 3: Copper & Laminate Upgrade | Specify VLP or HVLP smooth copper foil | Cuts high-frequency roughness attenuation significantly | Moderate material premium; standard processing on most high-speed lines | Recommended when operating above 10–14 GHz Nyquist |
| Tier 3: Copper & Laminate Upgrade | Upgrade from standard FR-4 to Mid-Loss or Low-Df laminate | Substantially lowers dielectric attenuation slope across all frequencies | Highest impact on raw material cost and lead time (subject to stock) | Necessary for long traces or 25G/56G/112G+ PAM4 channels |
Note that widening a trace only reduces attenuation if the dielectric height to the reference plane increases proportionally to hold the target differential impedance (commonly 85 Ω, 90 Ω, or 100 Ω). If a trace is widened without increasing dielectric thickness, impedance drops and creates reflection losses. Coordinating High Speed PCB stackup and material selection early with your fabrication partner ensures that target trace widths, dielectric thicknesses, and available laminate cores align with real manufacturing tolerances.
Frequently Asked Questions
At what data rate does PCB signal attenuation become critical?
Signal attenuation typically requires formal budget modeling once per-lane data rates reach 5 Gbps to 10 Gbps (Nyquist frequencies of 2.5 GHz to 5 GHz), particularly when trace lengths exceed several inches or pass through connectors. Below 3 Gbps, trace resistance and dielectric losses are usually minor compared to reflection and crosstalk concerns unless cables or very long backplanes are involved.
Does widening a PCB trace always reduce insertion loss?
Widening a trace reduces conductor resistance and skin-effect loss, but only if the stackup’s dielectric thickness is increased at the same time to maintain constant characteristic impedance. Furthermore, on ultra-long channels where dielectric dissipation dominates over conductor loss, widening the trace yields diminishing returns compared to switching to a lower-Df laminate.
How does fiberglass weave effect interact with signal attenuation?
Standard woven fiberglass cloth consists of glass bundles (Dk ≈ 6) separated by resin-rich gaps (Dk ≈ 3). When one leg of a differential pair runs over a glass bundle and the other runs over resin, the two signals propagate at different velocities, creating intra-pair skew. This timing skew converts differential signal energy into common-mode noise, which further degrades the differential insertion loss (SDD21) at high frequencies. Using spread-glass weaves (such as 1067 or 1078 styles) or rotating the routing angle mitigates this effect.
What information does a PCB manufacturer need to validate a loss-sensitive stackup?
To verify stackup feasibility and impedance accuracy, provide your fabricator with the layer count, target board thickness, target single-ended and differential impedance values (e.g., 50 Ω and 100 Ω), minimum trace width/spacing, and your maximum allowable attenuation target (in dB/inch at a specified test frequency). Sharing preferred laminate families or dissipation factor limits also helps engineers recommend stocked cores that avoid procurement delays.
Validate Your Multi-Gigabit Stackup Before Fabrication
Calculating a theoretical loss budget is only half of the engineering workflow; ensuring that the manufactured board matches your simulation model requires tight control over dielectric thickness, copper foil roughness, etching compensation, and via stub removal. Unverified stackup substitutions or overly rough copper foils can consume several decibels of margin before a prototype ever reaches the test bench.
Before finalizing your layout or releasing Gerber files for production, prepare the following parameters for engineering review:
- Interface Protocol & Nyquist Frequency: Target data rate (e.g., 10G, 25G, 56G, or 112G) and evaluation frequency.
- Impedance & Loss Targets: Required differential impedance profiles and maximum dB/inch insertion loss ceiling.
- Physical Constraints: Layer count, finished board thickness, and any blind, buried, or backdrilled via requirements.
Planning a multi-gigabit interface and need to verify whether your stackup meets its channel budget? Submit your stackup specifications, target impedance, and loss constraints to the Mars PCB Innotech engineering team through our High Speed PCB manufacturing services page for a pre-production material and DFM feasibility review.
Key Takeaways
- Insertion loss (S21) acts as a frequency-dependent filter: In multi-gigabit links, high-frequency harmonics attenuate faster than fundamental frequencies, causing edge degradation and inter-symbol interference (ISI).
- Four mechanisms drive channel attenuation: Dielectric dissipation (Df), skin-effect conductor resistance, copper foil surface roughness, and impedance discontinuities (vias/connectors) all subtract from signal amplitude.
- Always budget from die to die: Deduct IC packages, connectors, vias, and a 10%–15% environmental/process margin from the SerDes allowance before calculating maximum allowable PCB trace length.
- Optimize geometry before over-specifying laminates: Shortening traces, adjusting trace-to-dielectric geometry, and backdrilling via stubs often recover critical decibels without the cost of exotic substrates.
- Verify copper profile alongside Df: Above 10 GHz, specifying VLP or HVLP smooth copper foil is often just as critical to meeting insertion loss targets as selecting a low-loss resin system.
