The transition from Non-Return-to-Zero (NRZ) to 4-Level Pulse Amplitude Modulation (PAM4) is the defining boundary in modern high-speed digital engineering. While NRZ has served as the baseline modulation scheme for generations of serial links, physical channel loss at frequencies above 28 GHz makes scaling NRZ to 56 Gbps, 112 Gbps, and beyond impractical over standard copper channels. PAM4 addresses this throughput barrier by packing two bits into every symbol period, effectively halving the required Nyquist frequency for a given data rate.

However, this bandwidth conservation introduces severe physical-layer penalties. By dividing the signal amplitude into four discrete voltage levels rather than two, PAM4 sacrifices roughly 9.5 dB of signal-to-noise ratio (SNR) and compresses usable eye heights to one-third of an NRZ signal. For engineering teams, PAM4 vs NRZ PCB design shifts the focus from basic digital continuity to microscopic transmission-line physics. Achieving channel compliance requires rethinking dielectric material selection, tightening trace impedance tolerances, eliminating via stubs, and coordinating closely with your fabricator to address surface roughness and weave skew.

The Bandwidth Crossroads: Why NRZ Is Yielding to PAM4 in Next-Gen PCB Design

NRZ is a binary modulation scheme that transmits one bit per unit interval (UI) using two signal levels: logic 0 and logic 1. At 28 Gbps, an NRZ transmission line operates at a Nyquist frequency of 14 GHz. Attempting to push NRZ to 56 Gbps or 112 Gbps forces the Nyquist frequency to 28 GHz and 56 GHz, respectively. At these extreme frequencies, standard FR-4 and mid-loss laminates exhibit severe dielectric absorption, copper skin-depth losses increase dramatically, and channel reach drops to a few inches.

The Electrical Reality: Why PAM4 Shrinks Your Margin for Error

Understanding the electrical vulnerabilities of PAM4 is necessary to establish realistic routing and stackup guidelines. Because the overall voltage swing remains constrained by receiver silicon limitations—typically around 800 mV to 1 V peak-to-peak—dividing this range into four distinct states creates three vertical eye openings.

The 9.5 dB SNR Penalty and Vulnerability to Crosstalk

In an ideal four-level signal where levels are evenly spaced, the vertical separation between adjacent levels is one-third of the total swing (1/3 ≈ -9.54 dB). This structural reduction in signal amplitude directly translates into an immediate 9.5 dB SNR deficit at the receiver slicer.

Because the signal margin is reduced by roughly 66%, noise sources that were negligible in NRZ architectures can completely close a PAM4 eye:

Far-End Crosstalk (FEXT) and Near-End Crosstalk (NEXT): Unshielded parallel runs or tightly spaced differential pairs couple energy that easily swamps the compressed eye height.

Power Distribution Network (PDN) Ripple: High-frequency switching noise on SerDes power rails directly translates into transmitter output jitter and vertical eye compression.

Intersymbol Interference (ISI): Reflections caused by downstream impedance variations collide with the attenuated inner eyes, preventing receiver decision feedback equalizers (DFE) from locking onto the transitions.

Multi-Eye Dynamics: Jitter, Slew Rates, and Reflection Sensitivity

Unlike NRZ, which features single, symmetrical rising and falling transitions, PAM4 features twelve distinct transition types between its four voltage levels.

PAM4 produces twelve distinct transition types between its four levels — versus a single transition in NRZ — multiplying the jitter and slew-rate profiles a receiver must tolerate.

Furthermore, return loss (reflections) becomes critical. In an NRZ system, a reflection generating -20 dB of return loss might consume only a fraction of the noise budget. In a PAM4 system, that same reflection magnitude can consume the entire eye opening, resulting in an uncorrectable bit error rate (BER) before Forward Error Correction (FEC) can recover the data. Maintaining continuous reference paths and controlled transitions is essential to satisfy  high-speed signal integrity standards.

Substrate and Material Engineering: Choosing the Right Dielectric for PAM4

Standard epoxy-glass substrates like conventional FR-4 are unsuitable for PAM4 links operating above 28 GBaud. Total channel attenuation is dominated by two physical mechanisms: dielectric loss (governed by the loss tangent, or dissipation factor, δ / D_f) and conductor loss (governed by the skin effect and copper profile).

For PAM4, board materials are categorized based on their dissipation factor at target frequencies:

Mid-Loss (D_f ≈ 0.010 – 0.015): Unsuitable for high-speed PAM4 channels exceeding a few inches.

Low-Loss (D_f ≈ 0.005 – 0.008): Viable for shorter board traces, onboard optical modules, or lower baud-rate applications.

Ultra-Low-Loss (D_f ≈ 0.002 – 0.004): Required for backplanes, server motherboards, and complex line cards handling 56G/112G PAM4. Materials based on modified polyphenylene ether (PPE/PPO) or fluoropolymer systems provide the necessary attenuation limits.

Beyond bulk loss, structural substrate balance is critical. Woven glass fabrics consist of fiberglass yarns (D_k ≈ 6.0) surrounded by resin matrix (D_k ≈ 3.0). If one leg of a differential pair routes directly over a dense glass knuckle while the companion trace routes over a resin-rich window, the phase velocities between the two lines diverge.

Specify spread-glass fabric styles (e.g., 1067, 1078, 3313) where glass filaments are mechanically flattened to eliminate resin windows.

Route critical high-speed differential pairs at an angle relative to the laminate weave (typically 10° to 12°), or specify an angled panelization layup during manufacturing.

Maintain symmetric dielectric thickness above and below stripline signal layers to balance field distribution.

Selecting appropriate core and prepreg systems requires balancing electrical performance and mechanical stability, reinforcing the importance of  low-loss laminate selection for high-speed PCBs during early stackup definition.

Copper Foil Roughness: Skin Effect at Millimeter-Wave Frequencies

At 14 GHz and 28 GHz, the skin depth of copper drops below 0.6 microns. As the current concentrates in this thin outer perimeter of the conductor, the microscopic profile (roughness) of the copper foil dictates the effective path length.

Untreated Standard Electrodeposited (ED) copper possesses deep surface peaks and valleys. When the root-mean-square surface roughness (R_q) exceeds the skin depth, current flows along the contours of the tooth structure rather than in a straight line, drastically increasing conductor loss and inducing phase delay variations.

Because PAM4 leaves minimal margin for reflection or phase degradation, standard high-speed layout rules must be tightened across geometry, stackup references, and vertical transitions.

Standard commercial PCBs typically target a ± 10% impedance tolerance. For a nominal 100 Ω differential trace, a variance of 10 Ω creates substantial reflection points along the transmission line.

For PAM4 designs, specify a differential impedance tolerance of ± 5%. Meeting this standard requires:

Adjusting trace widths to account for etching profiles and trapezoidal cross-sections.

Maintaining tight spacing between ground reference planes and signal conductors.

Selecting stripline configurations over microstrip to avoid inhomogeneous dielectric interfaces (air vs. substrate/solder mask).

Minimizing Discontinuities: Via Stubs, Backdrilling, and Antipads

A via stub acts as an unterminated transmission line dangling from the signal path. At its quarter-wavelength resonant frequency, the stub acts as an energy trap, creating a deep notch filter in the insertion loss profile (S₂₁).

For 56G/112G PAM4 signaling, an unmitigated via stub as short as 20 to 30 mils (0.5 – 0.75 mm) can create a resonant null directly within the operating frequency band, completely collapsing the signal.

Controlled Backdrilling: Fabricators must backdrill unneeded via barrels from the opposite side to leave a residual stub length of less than 0.2 mm (8 mils), with target thresholds under 0.15 mm for critical lines.

Blind and Buried Vias: For high-density interconnections, transition between sequential lamination microvias to eliminate through-hole stubs altogether.

Antipad Optimization: Enlarge antipads (clearances in ground planes beneath through-hole pads) to eliminate excess capacitive coupling between the pad and adjacent ground copper, matching the nominal transmission line impedance through the z-axis transition.

Trace Geometry, Bends, and Return Path Continuity

Curved or Loose Bends: Avoid sharp 90^ and standard 45^ mitered corners. Use curved routing or large, sweeping mitered arcs with a bend radius at least 3 to 5 times the dielectric height to prevent localized trace-width expansion and capacitive loading.

Ground Return Vias: Whenever a differential pair transitions between signal layers, place two ground transfer vias immediately adjacent to the signal via pair (within 20 to 30 mils). This ensures an uninterrupted, low-inductance return path through the reference planes and prevents high-frequency common-mode loop currents.

Manufacturing and DFM Considerations: What to Verify with Your Fabricator

A high-speed design simulated in an EDA environment is only as effective as the board fabricator’s process control. The tight geometry and material requirements of PAM4 demand active design-for-manufacturability (DFM) verification with your production partner prior to panelization.

Achieving ± 5% impedance requires tight control over core etching, prepreg glass flow, and inner-layer registration. Etch compensation must account for trace thinning on outer and inner copper layers.

Furthermore, during multi-layer lamination, inner-layer image displacement must be tightly controlled. Misregistration between signal layers and clearance antipads distorts via field impedance, introducing channel-to-channel crosstalk and phase variations.

Surface Finishes and Solder Mask Impact at High Frequencies

Liquid Photoimageable (LPI) solder mask is extremely lossy at microwave frequencies, exhibiting a high dissipation factor (D_f > 0.02). For this reason, high-speed PAM4 traces should be routed on internal stripline layers rather than outer microstrip layers.

Where outer traces or breakout pads must carry high-frequency signals, surface finish selection is critical:

Electroless Nickel Immersion Gold (ENIG): The electroless nickel layer (a ferromagnetic barrier roughly 3–5 microns thick) exhibits high bulk resistivity and magnetic permeability, causing severe conductor attenuation at frequencies above 10 GHz.

Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG): While providing structural assembly reliability, the underlying nickel still degrades insertion loss in direct high-speed paths.

Immersion Silver (IAg) or Organic Solderability Preservatives (OSP): Highly recommended for high-speed exposed conductors. Immersion silver deposits planar, non-magnetic metallic coatings directly onto the copper, preserving signal margins.

Fabrication Verification Checklist

Before releasing production panels, verify the following specifications with your manufacturing team:

• Etch Profile Compensation: Fabricator models trapezoidal etch factors to hit nominal impedance targets.
• Backdrill Depth Control: Production facility guarantees maximum residual stub length (< 0.2 mm or customer-specified threshold).
• Laminate Verification: Confirmation of specified ultra-low-loss core/prepreg brands, lot numbers, and spread-glass yarn styles.
• Copper Foil Specification: Verification of HVLP or VLP foil use on all high-speed inner layers.
• Coupon Testing Protocol: Inclusion of test coupons on every production panel for Time-Domain Reflectometry (TDR) and Vector Network Analyzer (VNA) S-parameter characterization.

Establishing these parameters early requires working with a partner capable of  precision high-speed PCB fabrication and backdrilling to ensure physical tolerances match the simulation model.

Key Takeaways

• Modulation Shift: PAM4 packs 2 bits per symbol to halve the required Nyquist frequency relative to NRZ at the same bit rate, preventing extreme high-frequency dielectric losses in links operating at 56G, 112G, and beyond.
• Reduced SNR Margins: Splitting the voltage swing into four discrete levels reduces the signal-to-noise ratio by approximately 9.5 dB and shrinks vertical eye height to one-third of an NRZ signal, increasing vulnerability to crosstalk and reflection.
• Substrate Engineering: Standard FR-4 is unsuitable for high-speed PAM4. Designs require ultra-low-loss resins (D_f ≤ 0.004), spread-glass fabrics to mitigate fiber weave skew, and HVLP copper foil to minimize skin-effect attenuation.
• Discontinuity Mitigation: Impedance variations must be held within ± 5%. Through-hole via stubs must be backdrilled to less than 0.2 mm residual length, and differential layer transitions require adjacent ground return vias to avoid resonant signal degradation.
• Fabrication Partnerships: Advanced high-speed layouts depend on tight manufacturing controls, including inner-layer registration, non-nickel surface finishes (such as Immersion Silver or OSP), and panel-level coupon testing via TDR and VNA.